1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for manufacturing semiconductor devices with reduced critical dimensions.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. All other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. The ability to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, is limited by, among other things, physical limits imposed by photolithography. Diffraction and reflection effects impose limits on the critical dimensions of components such as gate conductors and gate dielectrics.
One conventional approach to achieving reduced critical dimensions involves placing an inorganic bottom anti-reflective coating (BARC) beneath a layer of photoresist to reduce reflections and refractions during the photolithographic process. Silicon oxynitride is one type of BARC typically used in semiconductor processing. Ordinarily, the silicon oxynitride layer is formed in an atmosphere that includes silane (SiH4) and nitrous oxide (N2O). Typically, a desirable ratio of silane and nitrous oxide that provides desirable optical properties, such as the refractive index (n) and extension coefficient (k), is determined empirically or experimentally, and thereafter, the process attempts to hold the determined ratio constant so that the optical properties, n and k, will remain constant also.
However, factors other than the ratio of silane and nitrous oxide also impact the optical properties, n and k. The silicon oxynitride layer is typically formed in a semiconductor processing tool, such as a deposition chamber. Variations within the chamber can impact the optical properties of the silicon oxynitride. For example, an abrupt variation in the optical properties, n and k, has been observed following servicing of the tool. In particular, an insitu cleaning of the chamber can have a significant impact on the optical properties, n and k. These variations in optical properties can result in variations in the quality of semiconductor products produced.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method is used to control a semiconductor processing tool. The method includes forming a first layer above a substrate layer, and forming an inorganic bottom antireflective coating layer above the first layer by introducing at least two gases at a preselected ratio into the semiconductor processing tools. A signal indicating that the semiconductor processing tool has been serviced is received, and the ratio of the gases is varied in response to receiving the signal.